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Grant: Strategic Projects - Group

University of Alberta

$100,000.00

Optimized design verification methodology of variation-tolerant Nanoscale systems

FY 2014-15

Summary
Integrated circuit (IC) technology has improved dramatically in performance due to continued miniaturization of the transistors and wiring. However, as the minimum feature size shrinks below 32 nm, it becomes very difficult to ensure that all defect-free fabricated chips will work correctly despite unavoidable variations in the process parameters, voltage conditions and operating temperature (that is, PVT variations). The Canadian start-up Solido Design Automation Inc. has developed industry-leading design software that allows engineers to efficiently select, from many thousands of PVT scenarios, the worst-case conditions that need to be verified in simulation. An initial objective of this research project is to establish a mutually beneficial collaboration between University of Alberta researchers and Solido to investigate improved methods for verifying the correct operation of ICs in the presence of PVT variations. The ultimate original objective of the project is to develop a comprehensive design methodology supporting the formation of new effective tools aimed at the identification of worst-case PVT corners and a design of a suite of algorithms as well as circuit benchmarks. As a long-term strategic goal, we will form a sustainable, world class research center focused on innovative optimized design of PVT variation-oriented verification methodology, by coordinating with world class researchers and bring in other Canadian companies. The comprehensive expertise of the research team is multifaceted and fully covers the needs arising from the proposed research project. The developed methodology is not only suitable for the design of current systems but it is far fetching and goes beyond the boundaries of the current components. In emerging nonconventional nanotechnologies, nondeterministic behaviours become profoundly visible and associated with quantum effects, environmental noise and, in some cases, inexpensive but inaccurate molecular self-assembly. Therefore, variation resilience must be incorporated into any nanoscale system design. In this sense the proposed methodologies will be applicable to the design of emerging ICT systems and will benefit the Canadian industry in a long term.
Program
Strategic Projects - Group
Location
Alberta, Canada
Recipient Type
Academia
Type
Grant
Source
NSERC's Awards Data

As published

Application id
447513-2013
Name nom
Han, Jie
Department département
Electrical and Computer Engineering
Organization id
9
Institution établissement
University of Alberta
Province en
Alberta
Province fr
Alberta
Country en
CANADA
Country fr
CANADA
Fiscal year exercice financier
2014
Competition year année de concours
2013
Award amount
100000
Program id
STPGP
Program name en
Strategic Projects - Group
Program name fr
Projets stratégiques - De groupe
Group en
Research partnerships programs
Group fr
Programmes de partenariat
Committee code
1567
Committee name en
Strategic Projects Selection Panel - ICT
Committee name fr
Comité de sélection des projets stratégiques - ICT
Area of application code
1207
Area of application group en
Advancement of knowledge
Area of application group fr
Avancement des connaissances
Area of application en
Information, computer and communication technologies
Area of application fr
Technologie de l'information, des ordinateurs et des réseaux de communications
Research subject code
2506
Research subject group en
Electrical and electronic engineering
Research subject group fr
Génie électrique et électronique
Research subject en
Electron devices
Research subject fr
Dispositifs électroniques
Partie
2
Nb partie
3
Application title
Optimized design verification methodology of variation-tolerant Nanoscale systems
Keyword
NSERC
Application summary
Integrated circuit (IC) technology has improved dramatically in performance due to continued miniaturization of the transistors and wiring. However, as the minimum feature size shrinks below 32 nm, it becomes very difficult to ensure that all defect-free fabricated chips will work correctly despite unavoidable variations in the process parameters, voltage conditions and operating temperature (that is, PVT variations). The Canadian start-up Solido Design Automation Inc. has developed industry-leading design software that allows engineers to efficiently select, from many thousands of PVT scenarios, the worst-case conditions that need to be verified in simulation. An initial objective of this research project is to establish a mutually beneficial collaboration between University of Alberta researchers and Solido to investigate improved methods for verifying the correct operation of ICs in the presence of PVT variations. The ultimate original objective of the project is to develop a comprehensive design methodology supporting the formation of new effective tools aimed at the identification of worst-case PVT corners and a design of a suite of algorithms as well as circuit benchmarks. As a long-term strategic goal, we will form a sustainable, world class research center focused on innovative optimized design of PVT variation-oriented verification methodology, by coordinating with world class researchers and bring in other Canadian companies. The comprehensive expertise of the research team is multifaceted and fully covers the needs arising from the proposed research project. The developed methodology is not only suitable for the design of current systems but it is far fetching and goes beyond the boundaries of the current components. In emerging nonconventional nanotechnologies, nondeterministic behaviours become profoundly visible and associated with quantum effects, environmental noise and, in some cases, inexpensive but inaccurate molecular self-assembly. Therefore, variation resilience must be incorporated into any nanoscale system design. In this sense the proposed methodologies will be applicable to the design of emerging ICT systems and will benefit the Canadian industry in a long term.