Grant: Discovery Grants Program - Individual

Transistor performance in the 90nm and below technologies is strongly affected by extrinsic layout-dependent effects (LDEs), such as transistor well proximity and stress effects. Recent research has shown that ignoring LDEs at nanometer process nodes can cause 15%-30% variation in the transistor performance, which may readily lead to malfunction of analog/RF integrated circuits (IC). When using leading-edge commercially available analog/RF design methodologies, the associated LDE impact on circuit performance is unknown before the layout is generated. Thus, a large number of design iterations as well as manual intervention are inevitably required in advanced technologies. In this research program, synergistic synthesis methodologies and computer-aided design tools will be studied to make a fusion between performance optimization and physical effects. An LDE- and variation-aware circuit topology synthesis methodology, which can effectively explore the search space proactively by considering associated layout impact, will be developed. A novel two-stage LDE-, variation- and parasitic-aware circuit- sizing methodology, which first deploys a symbolic-equation-based scheme for quick global optimization and then a simulation-based method for refined sizing, will be studied. We will also investigate automatic layout synthesis strategies to address LDE-, variation- and parasitic-related constraints. Analog/RF ICs have been recognized as the design bottleneck for promptly pushing mixed-signal system-on- chip products to market due to high sensitivity to the complicated analog effects. Systematic countermeasures in the LDE-aware synthesis of analog/RF ICs have not yet been addressed worldwide. With enormous potential for commercialization, this proposed research program addresses the increasingly challenging LDE problems and their profound interactive nature that cannot be ignored for analog/RF IC synthesis in nanometer technolo- gies. This program will benefit the analog/RF design community through significant improvements in design productivity and reliability, and will enhance Canada's competitive advantage in this field.