Grant: Discovery Grants Program - Individual

Realization of robust integrated circuits in state of the art technologies is becoming increasingly difficult. The technology scaling makes transistors susceptible to process variations, and improper functioning of a single transistor may lead to the chip failure containing several million transistors. Often small as possible transistor sizes are used to reduce power, energy consumption, and to increase the packing density. Unfortunately, transistors with smaller dimensions exhibit a higher susceptibility to process variation. In particular, low-voltage, low-power Static Random Access Memory (SRAM) circuits show higher degree of variation owing to smallest possible transistor dimensions. In this research, we will investigate variability-aware design of digital, SRAM circuits in power and voltage constrained environments. In microprocessors up to 70-80% of transistors are in SRAMs. As a consequence, various aspects of Systems on Chip (SoC) - power, energy, yield, quality, and reliability are influenced by SRAMs. The proposed research has two broad segments - (a) SRAM circuits, and (b) logic circuits. In the first segment, few aspects of SRAMs will be investigated. The key objectives of this research are (i) to lower SRAM power consumption through architectural and circuit innovation. We will design functional SRAMs working at sub-threshold voltages. (ii) To devise circuit techniques to alleviate the impact of process variations on important SRAM blocks such as the sense amplifier. We will investigate new architectures and circuits for the sense amplifier. (iii) Design soft error robust SRAM cells that can recover from single event upsets. In the second segment of the research, we will investigate high speed digital circuits working at the nominal voltage. Research on high speed circuits will entail investigation of high speed logic styles. This work builds on our recent research on Constant Delay (CD) logic style. Building blocks such as adder will be designed to demonstrate effectiveness of new logic families for high-speed applications.