Grant: Discovery Grants Program - Individual

Despite good progress in the last 2 decades of development, the leading-edge analog (including radio frequency (RF)) and mixed-signal (AMS) integrated circuit (IC) commercial design automation products are still a stack of relatively separate design stages mainly focusing on circuit simulation/sizing and layout generation. There are scarce off-the-shelf offerings for AMS topology synthesis at both circuit and system levels, not to mention in the context of layout and manufacturability awareness. Recently, artificial intelligence (AI) has demonstrated an admirable capability in solving complex problems ranging from computer games (e.g., AlphaGo) to large language models (e.g., ChatGPT). AI is now opening doors to the full automation of AMS design, which traditionally has been confined to an experienced human designer's job because learning analog circuit design is well recognized to take years to get started and decades to master. In this research program, the fascinating advancement of AI will be leveraged to promote electronic design automation (EDA) of AMS ICs. A set of synthesis methodologies and computer-aided design tools will be studied to strengthen the link between high-level electrical performance optimization and low-level physical effects. An innovative hierarchical reinforcement-learning-(RL)-driven circuit topology synthesis methodology will be developed for the analog functional modules (e.g., operational amplifiers and comparators). Complex circuit structures (e.g., feedback and current split) will be supported along with the countermeasures against layout and manufacturability impacts. Moreover, a novel AMS system-level topology synthesis methodology will be studied; this methodology will be based on multi-agent RL and broad-explainable-AI for addressing the multi-objective and high dimensionality issues. Furthermore, a layout-inclusive RF circuit synthesis methodology will be explored to strengthen the integration between electrical synthesis (including circuit topology and layout-aware sizing) and layout synthesis (via layout migration and optimization). Due to high sensitivity to intricate analog effects and large complexity in the performance search space, automated synthesis of AMS IC has been recognized as a bottleneck for promptly pushing system-on-chip products to market. The AMS layout-aware circuit-level and system-level syntheses have not yet been addressed worldwide. With enormous commercialization potential, this proposed program addresses the low synthesis efficiency and limited generality issues, promoting knowledge fusion of topology-sizing-layout towards joint optimizations in the advanced nanometer technologies. It will involve the training of 9 next-generation highly qualified personnel (HQP) on advanced EDA and automated AMS design. This will benefit the AMS design community through significant improvements in design productivity and reliability, which can enhance Canada's competitive advantage in this field.