Grant: Collaborative Research and Development Grants

Data centers are typically built on Ethernet networks to benefit from low cost of Ethernet devices. However, Ethernet suffers from crucial traffic engineering capability shortage in terms of data packet loss and latency while consolidating servers in dense data centers needs careful resource management. On the other hand, the combination of cloud computing with mobile ad-hoc networks in 5G will clearly build new prevailing networks by supporting a large number of different bandwidth-hungry applications with bursting data, such as real-time search and data analysis. Furthermore, 5G networks are expected to provide exponentially more capacity, lower latency, ubiquitous connectivity, as well as increased reliability and availability. The erratic property of data center traffic makes 5G requirements quite challenging and necessitates the design of innovative congestion control mechanisms. Hence, the ultimate goal is to propose an end-to-end congestion control solution for 5G networks, from data center end-host to end-users. The objective of this UQAM-NSERC-Prompt Québec collaborative project between is to improve network bandwidth sharing between hosts in data centers, by proposing innovative congestion control schemes with minimal modifications of commodity switches hardware. Thus, we are proposing to investigate different congestion control approaches seemly to the 5G networks paradigm. We propose the design and the study of new Ethernet Fabric congestion control schemes involving different components of data centers (Hosts, switches). We are also proposing transport layer enhancement to build a comprehensive end-to-end congestion control in 5G networks solution. Furthermore, to assess our proposed congestion control schemes, we are using rigorous performance evaluation methods. Indeed, we will build a web-scale data center network simulator to be used at the first phase of performance evaluation. Afterward, a Linux-based network emulator will be developed to perform more realistic tests and experimentations. Also, our proposed modification involving the switch will be implemented and tested in a FPGA environment.