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Grant: Research Tools and Instruments - Category 1 (<$150,000)

Carleton University

$80,804.00

FPGA prototyping system for error floor analysis and digital implementation of iterative decoders

FY 2009-10

Summary
Error correction coding is an essential part of any communication system. It allows reliable transmission of information over communication channels such as Internet, wireless, cellular, optical and satellite links. It also allows for reliable retrieval of information from storage devices such as hard drives, CDs and DVDs. To evaluate the error rate performance of a coding scheme, Monte Carlo simulations based on software are often used. For a reliable estimation of error rates, the reach of such simulations however is limited to rather high error rates of about 10^(-7). To reach error rates of order 10^(-10), even with the state-of-the-art computers, would take days. This is while for some applications such as optical communications and storage devices, error rates down to 10^(-15) are required. This is simply out of the reach of software Monte Carlo simulations. In such cases, hardware simulations have to be used. This proposal is for a hardware prototyping system that will be used to analyze the error rate performance of the state-of-the-art coding schemes, such as low-density parity-check (LDPC) codes, at very low error rates. The system will support our on-going research on the design, analysis and implementation of high-performance LDPC codes in applications where low error rates are required. The outcome of this research will give Canada a competitive edge in providing advanced error correction solutions for a variety of applications.
Program
Research Tools and Instruments - Category 1 (<$150,000)
Location
Ontario, Canada
Recipient Type
Academia
Type
Grant
Source
NSERC's Awards Data

As published

Application id
390838-2010
Name nom
Banihashemi, Amir
Department département
Systems and Computer Engineering
Organization id
23
Institution établissement
Carleton University
Province en
Ontario
Province fr
Ontario
Country en
CANADA
Country fr
CANADA
Fiscal year exercice financier
2009
Competition year année de concours
2010
Award amount
80804
Program id
EQPEQ
Program nane en
Research Tools and Instruments - Category 1 (<$150,000)
Program name fr
Outils et instruments de recherche - catégorie 1 (<150 000$)
Group en
Discovery grants programs
Group fr
Programmes de subventions à la découverte
Committee code
1510
Committee name en
Electrical and Computer Engineering
Committee name fr
Génie électrique et informatique
Area of application code
805
Area of application group en
Information and communication services
Area of application group fr
Services d'information et de télécommunications
Area of application en
Communications technologies (satellites, radar, etc.)
Area of application fr
Technologie des télécommunications (satellites, radar,etc.)
Research subject code
2507
Research subject group en
Electrical and electronic engineering
Research subject group fr
Génie électrique et électronique
Research subject en
Communications systems
Research subject fr
Systèmes de télécommunications
Partie
1
Nb partie
1
Application title
FPGA prototyping system for error floor analysis and digital implementation of iterative decoders
Keyword
NA
Application summary
Error correction coding is an essential part of any communication system. It allows reliable transmission of information over communication channels such as Internet, wireless, cellular, optical and satellite links. It also allows for reliable retrieval of information from storage devices such as hard drives, CDs and DVDs. To evaluate the error rate performance of a coding scheme, Monte Carlo simulations based on software are often used. For a reliable estimation of error rates, the reach of such simulations however is limited to rather high error rates of about 10^(-7). To reach error rates of order 10^(-10), even with the state-of-the-art computers, would take days. This is while for some applications such as optical communications and storage devices, error rates down to 10^(-15) are required. This is simply out of the reach of software Monte Carlo simulations. In such cases, hardware simulations have to be used. This proposal is for a hardware prototyping system that will be used to analyze the error rate performance of the state-of-the-art coding schemes, such as low-density parity-check (LDPC) codes, at very low error rates. The system will support our on-going research on the design, analysis and implementation of high-performance LDPC codes in applications where low error rates are required. The outcome of this research will give Canada a competitive edge in providing advanced error correction solutions for a variety of applications.