Grant: Discovery Grants Program - Individual
Lakehead University
$30,000.00
Power and performance optimization techniques for multi-core processors
FY 2011-12
Summary
Chip multiprocessors (CMPs) are becoming mainstream, making parallel programming necessary to utilize computational power provided by many cores. However, the grand challenge is to make parallelism pervasive and make it accessible for average programmers. The main difficulty of parallel programming comes from synchronization; concurrent accesses to a memory location should be coordinated to ensure that they do not interfere. This research proposal aims at improving power- and performance-efficiency of synchronization in chip multiprocessors.
Conventional lock-based programming can lead to deadlock, thread inversion, and other synchronization bugs which do not exist in sequential programs. These synchronization bugs are too challenging for most of programmers. A possible solution for lock-based synchronization is transactional memory (TM). With transactions, the programmer marks regions of a program that should execute atomically, and the runtime system ensures correctness of the application. While the programmer does not need to worry about synchronization bugs in TM, TM results in significant overhead in both hardware- and software-based implementation. Hardware transactional memory (HTM) needs special caches or buffers to keep track of speculative changes to data. These buffers and caches are new features that are not supported by existing hardware. On the other side, software transactional memory uses software support to manage speculative data within a transaction. While STM does not need any changes to existing hardware, it has significant performance overhead which is due to software support for implementation.
This research program contributes towards improving power and performance of locks and TMs in chip multiprocessors. While in short term, lock is the dominant synchronization method, TM is an attractive synchronization technique for future CMPs. Nevertheless, both locks and TMs incur significant power and performance overhead, and optimization techniques are required to reduce overhead of locks and TMs.
Program
Discovery Grants Program - Individual
Recipient
Location
Ontario, Canada
Recipient Type
Academia
Type
Grant
Source
NSERC's Awards Data
As published
Application id
372054-2009
Name nom
Atoofian, Ehsan
Department département
Electrical Engineering
Organization id
25
Institution établissement
Lakehead University
Province en
Ontario
Province fr
Ontario
Country en
CANADA
Country fr
CANADA
Fiscal year exercice financier
2011
Competition year année de concours
2009
Award amount
30000
Program id
RGPIN
Program nane en
Discovery Grants Program - Individual
Program name fr
Programme de subventions à la découverte - individuelles
Group en
Discovery grants programs
Group fr
Programmes de subventions à la découverte
Committee code
1079
Committee name en
Electrical and Computer Engineering
Committee name fr
Génie électrique et de l'informatique
Area of application code
1207
Area of application group en
Advancement of knowledge
Area of application group fr
Avancement des connaissances
Area of application en
Information, computer and communication technologies
Area of application fr
Technologie de l'information, des ordinateurs et des réseaux de communications
Research subject code
2719
Research subject group en
Information technology
Research subject group fr
Technologie de l'information
Research subject en
Computer architecture and design
Research subject fr
Architecture d'ordinateur et conception
Partie
3
Nb partie
5
Application title
Power and performance optimization techniques for multi-core processors
Keyword
NSERC
Application summary
Chip multiprocessors (CMPs) are becoming mainstream, making parallel programming necessary to utilize computational power provided by many cores. However, the grand challenge is to make parallelism pervasive and make it accessible for average programmers. The main difficulty of parallel programming comes from synchronization; concurrent accesses to a memory location should be coordinated to ensure that they do not interfere. This research proposal aims at improving power- and performance-efficiency of synchronization in chip multiprocessors.
Conventional lock-based programming can lead to deadlock, thread inversion, and other synchronization bugs which do not exist in sequential programs. These synchronization bugs are too challenging for most of programmers. A possible solution for lock-based synchronization is transactional memory (TM). With transactions, the programmer marks regions of a program that should execute atomically, and the runtime system ensures correctness of the application. While the programmer does not need to worry about synchronization bugs in TM, TM results in significant overhead in both hardware- and software-based implementation. Hardware transactional memory (HTM) needs special caches or buffers to keep track of speculative changes to data. These buffers and caches are new features that are not supported by existing hardware. On the other side, software transactional memory uses software support to manage speculative data within a transaction. While STM does not need any changes to existing hardware, it has significant performance overhead which is due to software support for implementation.
This research program contributes towards improving power and performance of locks and TMs in chip multiprocessors. While in short term, lock is the dominant synchronization method, TM is an attractive synchronization technique for future CMPs. Nevertheless, both locks and TMs incur significant power and performance overhead, and optimization techniques are required to reduce overhead of locks and TMs.
