Grant: Strategic Projects Supplemental Competition

Software Defined Radio (SDR) and Cognitive Radio (CR) technologies are propelling wireless communications by allowing seamless global service, interoperability and dynamic spectrum allocation. This project aims at investigating flexible, practical and cost and power efficient Digital Reconfigurable Radio (D2R) front-end architectures that can be adaptively tuned to support a broad range of frequencies and air interfaces through software programming. Since the transmitters' front-ends are generally the bottleneck of every radio system design, this project will mainly focus on the development of a novel cost effective and power efficient integrated software/hardware reconfigurable polar transmitter. The architecture design task shall first address issues such as optimum location of the Analog/Digital interface location, flexibility, power consumption and generic building blocks. These are assumed to be identified and their requirements derived. Another objective is to develop and fabricate high efficiency and switching mode reconfigurable power amplifiers in order to minimize the power consumption of the D2R. To enable the implementation of such switched mode PAs, low-loss, multi-harmonic and reconfigurable load transformation networks, using advanced RF electronically tuneable devices, will be investigated. Advanced digital signal processing (DSP) techniques will also be developed for proper modeling and linearization of the nonlinearity exhibited by reconfigurable polar transmitters, in order to satisfy the stringent linearity requirements of the wireless communication standards. In addition, sophisticated DSP techniques will be researched for dynamic reconfiguration of the analog circuitry of the digitally reconfigurable polar transmitter. This project will target wireless standards spanning from CDMA (3GPP-LTE) up to the most demanding OFDM based communication standards (802.11n, 802.16). Hence, a prototype, with carrier frequencies of up to 10GHz and modulation bandwidth of up to 20MHz, will be fabricated in order to assess the performance of the proposed digitally reconfigurable transmitter.