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Grant: Discovery Grants Program - Individual

University of Windsor

$51,000.00

Low Power, Area Efficient, High Speed Algorithms and Architectures for Computer Arithmetic, Pattern Recognition and Cryptosystems

FY 2015-16

Summary
The objectives of the proposed research are: (a) To further extend the state-of-the-art for the Finite Field Multiplication in F(2**m) for applications to elliptic curve cryptography. We will look at implementation for the proposed architectures as ASIC at the transistor level to reduce power consumption and to improve speed. We will also look at GPU configurations as a paradigm for implementation of our proposed architectures. (b) To further extend the state-of-the-art for the design, implementation and application of arithmetic circuits using the Continuous Valued Number System (CVNS).The application of this number system for multi-layer neural networks will be investigated. A thorough evaluation of the resulting next-generation circuit designs and their comparison with current state-of-the-art binary designs will be carried out. (c) To further develop robust and low error rate algorithms for pattern recognition applications. Specifically we are interested in applications such as human face recognition using new feature extractors and classifiers. We are looking into developing algorithms for face recognition under occlusion, varying or poor illumination and low resolution. We will be looking at the optimization of these algorithms for implementation on both GPU, for high speed operation, and low-power architectures. We shall further explore the development of new algorithms for face recognition with 3-D images. The development of algorithms and architectures that can support a face recognition capability on cellular smart phones that can be used to optimize functionality, security and power management based on visual cues will also be investigated. This research is considered significant as further progress in a number of diverse application areas beneficial to Canada is contingent upon developing competitive low-cost, low-power, high-speed area efficient DSP algorithms and architectures that enable synergy.
Program
Discovery Grants Program - Individual
Location
Ontario, Canada
Recipient Type
Academia
Type
Grant
Source
NSERC's Awards Data

As published

Application id
1686-2013
Name nom
Ahmadi, Majid
Department département
Electrical and Computer Engineering
Organization id
37
Institution établissement
University of Windsor
Province en
Ontario
Province fr
Ontario
Country en
CANADA
Country fr
CANADA
Fiscal year exercice financier
2015
Competition year année de concours
2013
Award amount
51000
Program id
RGPIN
Program name en
Discovery Grants Program - Individual
Program name fr
Programme de subventions à la découverte - individuelles
Group en
Discovery grants programs
Group fr
Programmes de subventions à la découverte
Committee code
1510
Committee name en
Electrical and Computer Engineering
Committee name fr
Génie électrique et informatique
Area of application code
513
Area of application group en
Manufacturing processes and products
Area of application group fr
Procédés et produits industriels
Area of application en
Electrical and electronic machinery and equipment (including computer hardware)
Area of application fr
Machinerie et équipement électriques et électroniques (y compris matériel informatique)
Research subject code
2514
Research subject group en
Electrical and electronic engineering
Research subject group fr
Génie électrique et électronique
Research subject en
Digital signal processing
Research subject fr
Traitement des signaux numériques
Partie
3
Nb partie
5
Application title
Low Power, Area Efficient, High Speed Algorithms and Architectures for Computer Arithmetic, Pattern Recognition and Cryptosystems
Keyword
NSERC
Application summary
The objectives of the proposed research are: (a) To further extend the state-of-the-art for the Finite Field Multiplication in F(2**m) for applications to elliptic curve cryptography. We will look at implementation for the proposed architectures as ASIC at the transistor level to reduce power consumption and to improve speed. We will also look at GPU configurations as a paradigm for implementation of our proposed architectures. (b) To further extend the state-of-the-art for the design, implementation and application of arithmetic circuits using the Continuous Valued Number System (CVNS).The application of this number system for multi-layer neural networks will be investigated. A thorough evaluation of the resulting next-generation circuit designs and their comparison with current state-of-the-art binary designs will be carried out. (c) To further develop robust and low error rate algorithms for pattern recognition applications. Specifically we are interested in applications such as human face recognition using new feature extractors and classifiers. We are looking into developing algorithms for face recognition under occlusion, varying or poor illumination and low resolution. We will be looking at the optimization of these algorithms for implementation on both GPU, for high speed operation, and low-power architectures. We shall further explore the development of new algorithms for face recognition with 3-D images. The development of algorithms and architectures that can support a face recognition capability on cellular smart phones that can be used to optimize functionality, security and power management based on visual cues will also be investigated. This research is considered significant as further progress in a number of diverse application areas beneficial to Canada is contingent upon developing competitive low-cost, low-power, high-speed area efficient DSP algorithms and architectures that enable synergy.
University of Windsor - $51,000 Grant (2015-16) | Canada Spends