Grant: Discovery Grants Program - Individual

As the conventional planar CMOS technology scales down to 22nm and below, maintaining ideal transistor characteristics becomes increasingly challenging. For this reason, nonplanar field-effect transistors (FETs) have been regarded as effective substitutes for ultimate scaling. Due to physical complexity of the nonplanar FET structure in advanced nanometer technologies, transistor performance is strongly affected by associated parasitics, layout dependent effects (LDEs), and lithographic imperfection. To maintain signal integrity, these issues have to be seriously considered in the synthesis of analog/RF integrated circuits (ICs).******In this research program, the fascinating advancement of artificial intelligence will be leveraged to promote electronic design automation (EDA) of analog/RF ICs. A complete set of synthesis methodologies and computer-aided design tools will be studied to strengthen the link between performance optimization and physical effects. An innovative machine-learning-driven circuit topology synthesis methodology will be developed. It can emulate expert human designers to apply the knowledge extracted from the given training data to effectively generate proper circuit topologies through inference. Moreover, a novel parasitic/LDE/lithography-aware circuit-sizing methodology will be studied; this methodology would consist of a quick approximate optimization stage followed by a simulation-based refined sizing process. Parasitics, LDEs, and lithographic effects in the advanced nonplanar nanometer technologies will be integrated into MOSFET modeling, which can be included into the topology synthesis and circuit sizing for proactive consideration of layout impact. Furthermore, to fill the vacuum of similar commercial tools in the EDA market, we will continue to explore automated analog/RF layout migration strategies to address parasitics, LDEs, and lithography-related constraints in the nonplanar nanometer technologies. ******Due to their high sensitivity to complicated analog effects, analog/RF ICs have been recognized as the design bottleneck for promptly pushing mixed-signal system-on-chip products to market. Systematic countermeasures in the layout-aware comprehensive synthesis of analog/RF ICs have not yet been addressed worldwide. With enormous potential for commercialization, this proposed research program addresses the increasingly challenging parasitics, LDEs, and lithographic issues in the nonplanar nanometer technologies; these issues cannot be ignored for analog/RF IC synthesis especially under the shrinking design window and pressing process variation. This program will train over half a dozen next-generation highly qualified personnel (HQP) on advanced EDA in upgraded nanometer technologies. It will benefit the analog/RF design community through significant improvements in design productivity and reliability, which can enhance Canada's competitive advantage in this field.**