Grant: Alliance Grants

The overall objectives of the collaborative project with Cisco Systems (Cisco) and Xiphos Systems (Xihos) are to develop fault-tolerant logic circuits fabricated with the most advanced Globalfundries (GF) 12nm FinFET technologies in order to reduce the soft error rate in partners' electronic products. The size of transistors in the modern integrated circuits (ICs) has been scaled to the nanometer range in modern commercial silicon technologies. As a result, ICs have become more vulnerable to single event effects (SEE) induced by energetic particles from either cosmic rays or packaging materials, which are normally referred to as soft errors. The project's main objectives are to characterize the single event effects in the 12nm FinFET process and develop/evaluate the redundant logic techniques to reduce the soft error rates in digital circuits. FinFET technologies have shown substantial reduction in soft error rate and power compared to bulk technologies, which makes them attractive in many industrial applications. There are two phases in this proposed collaborative project. In the first phase, various fault-tolerant storage components like flip-flops and logic gates will be designed and fabricated in a test chip with this technology. A radiation-tolerant standard cell library will also be developed. In the second phase, a fault-tolerant RISC-V microprocessor will be designed with the fault-tolerant standard cell library to evaluate their soft error performance. In each project phase, a test chip will be designed with the proposed test structures. Ion beams (heavy ions, neutron, and protons) will be used to evaluate the test structures' performance. The investigation will also use an on-campus pulsed laser facility to simulate the ion hits. In addition, device and circuit-level simulation tools will be utilized to model and characterize the test circuits' performance. The research will enable our industrial partner using the cost-effective technologies with the advantages (lower power, higher speed, etc.) of nanoscale CMOS technologies without compromising reliability and performance. Two PhD, one M.Sc, one undergraduate student and one postdoc fellow will be trained in this project alone with producing publications in the silicon reliability field.