Grant: Discovery Grants Program - Individual

Digital control is the heart of motion industry, and the associated algorithms can go from simple to more complex, with dynamics ranging from few microseconds to several tens of seconds. The need to perform complex computations with high real-time constraints has always been a major technological challenge for the development of advanced controllers. Thanks to major technological breakthroughs in recent years and sustained rapid progress in the areas of a massive scale integration and computer aided design tools, the realization of application specific chips becomes increasingly rapid and affordable, enabling electronic systems to cross new performance records. The reconfigurable FPGA permits now to design and validate quickly, in laboratory, any SoC. For low production volumes (few 1000s), the FPGA is economically advantageous as a final platform. For higher volume production, the description in the form of ""netlist"" of FPGA-based prototype of the controller can then be sent to an ICs fabric to be etched in silicon as an ASIC. However, as these new technologies are beginning to be used in digital control to overcome the limitations of microcontrollers and DSP processors used so far, new challenges are emerging due to several factors, including the difficulty for control specialists to work easily with these technologies, lack of design tools adapted for their needs, the increasing complexity of control algorithms to meet exigent dynamic, and the difficulty of implementing them in the form of ICs. The need for a research contribution to assist the development of generalized system on a chip for digital control is therefore felt. To meet this need, the main objective of the present proposal is to design and develop an effective technology that includes an easy design strategy and reusable hardware cores that are well adapted to both the user and performance criteria of the application. An FPGA platform will be used to support the proposed technology targeting real-time constraints no more than ten microseconds while keeping a low to moderate logic space for a cost-effective solution. The functionality and performance of this contribution will be demonstrated through some case studies of complex control AC drives.