Grant: Strategic Projects Supplemental Competition

Programmable hardware in the form of field-programmable gate array (FPGA) technology is a vital technology invented nearly 25 years ago for implementing digital hardware systems. The key strengths of the technology are nearly instant manufacturing, no up-front manufacturing costs, and the ability to alter the hardware to fix bugs or add features at no cost. While research on improving FPGA density, speed, and power continues to be influential, it is beginning to plateau. Very large or very fast digital circuits are still designed as custom circuits, called ASICs, even though this option is becoming prohibitively costly. A revolutionary approach is needed to extend FPGAs into realm of being bigger and faster than they are currently. This research is about radically changing FPGA architecture so it can implement much larger and much faster systems on one chip. This will be done by combining two techniques: 1) replacing much of the inefficient, single-bit logic and interconnect with more efficient, multi-bit datapath logic and interconnect, and 2) time-multiplexing the datapath logic at a much higher clock rate in the same way a CPU re-uses its ALU to perform arithmetic and logical operations. The key reason why this will work is that large FPGAs and most ASICs are used to build highly-parallel computational systems for tasks like digital signal processing. Long ago, FPGAs were once targeted at small amounts of glue logic that required bit-level configurability. However, they are now used to perform word-oriented calculations that cannot be done quickly enough with a conventional CPU or DSP processor. By increasing the capacity of FPGAs, they will be able to perform such computations with more parallelism, hence more performance, than they can today.