Grant: Collaborative Research and Development Grants
University of Saskatchewan
$69,738.00
Logic in-Field Repair and Soft Error Characterization for Microelectronics Reliability
EF 2011-12
Résumé
Over the last four decades, silicon technology scaling has remarkably improved the integrated circuits (ICs) by increasing the transistor density and operating frequency while reducing the cost and energy consumption per transistor. However, scaling in the sub-65 nanometer regime has brought a number of reliability issues. In particular, due to the small device dimension and low operating voltages, nanoscale ICs show more sensitive to operational disturbances, reduced reliability margin and wear-out lifetimes. In addition, the scaling of silicon technology also makes ICs more vulnerable to single event effects (SEE) induced by energetic particles. In a well-designed IC, soft errors induced by SEE appear to be the most troublesome both in terrestrial and high altitude or space environment. In this proposal, built-in self-repair combined with built-in self-test methods will be developed to enable ICs to self-diagnose and self-repair hard failures during field operations. The developed methods will be implemented with advanced complimentary metal oxide semiconductor (CMOS) technologies to evaluate their effectiveness. The soft errors will also be characterized and modeled through the 40nm CMOS test chips provided by the industrial partner. Laser and 3-D Technology Computer Aided Design (TCAD) simulation tools will be used for the investigation, so that SEE mitigation methods can be effectively developed. The Canadian industry partner (Cisco Canada) can directly adopt the technologies developed from this project to improve the lifetime and reliability of their produces such as switches and linecards, which can significantly improve the performance and reduce the maintenance cost. The project will also enhance the capability and expertise of the research group in the area of microelectronics reliability at the University of Saskatchewan. In this project, one M.Sc., one Ph.D., one postdoctoral fellow and two summer students will be trained to advance the technology and to work closely with the industrial partners.
Programme
Collaborative Research and Development Grants
Bénéficiaire
Emplacement
Saskatchewan, Canada
Type de bénéficiaire
Academia
Type
Grant
Source
NSERC's Awards Data
Tel que publié
Application id
413623-2011
Name nom
Chen, Li
Department département
Electrical & Computer Engineering
Organization id
16
Institution établissement
University of Saskatchewan
Province en
Saskatchewan
Province fr
Saskatchewan
Country en
CANADA
Country fr
CANADA
Fiscal year exercice financier
2011
Competition year année de concours
2011
Award amount
69738
Program id
CRDPJ
Program nane en
Collaborative Research and Development Grants
Program name fr
Subventions de recherche et développement coopérative
Group en
Research partnerships programs
Group fr
Programmes de partenariat
Committee code
96
Committee name en
RPP Internal Decision Cttee
Committee name fr
Cté de décision interne - PPR
Area of application code
514
Area of application group en
Manufacturing processes and products
Area of application group fr
Procédés et produits industriels
Area of application en
Communications equipment
Area of application fr
Matériel de télécommunications
Research subject code
2506
Research subject group en
Electrical and electronic engineering
Research subject group fr
Génie électrique et électronique
Research subject en
Electron devices
Research subject fr
Dispositifs électroniques
Partie
1
Nb partie
2
Application title
Logic in-Field Repair and Soft Error Characterization for Microelectronics Reliability
Keyword
NSERC
Application summary
Over the last four decades, silicon technology scaling has remarkably improved the integrated circuits (ICs) by increasing the transistor density and operating frequency while reducing the cost and energy consumption per transistor. However, scaling in the sub-65 nanometer regime has brought a number of reliability issues. In particular, due to the small device dimension and low operating voltages, nanoscale ICs show more sensitive to operational disturbances, reduced reliability margin and wear-out lifetimes. In addition, the scaling of silicon technology also makes ICs more vulnerable to single event effects (SEE) induced by energetic particles. In a well-designed IC, soft errors induced by SEE appear to be the most troublesome both in terrestrial and high altitude or space environment. In this proposal, built-in self-repair combined with built-in self-test methods will be developed to enable ICs to self-diagnose and self-repair hard failures during field operations. The developed methods will be implemented with advanced complimentary metal oxide semiconductor (CMOS) technologies to evaluate their effectiveness. The soft errors will also be characterized and modeled through the 40nm CMOS test chips provided by the industrial partner. Laser and 3-D Technology Computer Aided Design (TCAD) simulation tools will be used for the investigation, so that SEE mitigation methods can be effectively developed. The Canadian industry partner (Cisco Canada) can directly adopt the technologies developed from this project to improve the lifetime and reliability of their produces such as switches and linecards, which can significantly improve the performance and reduce the maintenance cost. The project will also enhance the capability and expertise of the research group in the area of microelectronics reliability at the University of Saskatchewan. In this project, one M.Sc., one Ph.D., one postdoctoral fellow and two summer students will be trained to advance the technology and to work closely with the industrial partners.