Grant: Collaborative Research and Development Grants
University of Saskatchewan
$75,453.00
On-chip voltage regulation in advanced technologies
EF 2018-19
Résumé
The scaling of silicon technologies has enabled multi-billions of transistors in a single chip, which increases the transistor density and operating frequency of the electronics while reducing the cost and energy consumption per transistor. However, this also imposes a significant challenge in power conversion, delivery and management with minimal power loss and noise. For example, only a fraction of the transistors on a large integrated circuit can operate at full voltage/frequency to not exceed the thermal design power, and a large proportion of the circuit blocks is either inactive or in a reduced-power state at any given time to satisfy the power and thermal constraints. This utilization limitation has urged the semiconductor community to develop more efficient power conversion and distribution circuits. The overall objectives of the research project are to optimize voltage regulator-converter circuits and power distribution networks to minimize the power loss during voltage conversion and the noise throughout the power delivery network in power management. The given objectives require power management circuit to be on the same die and optimized together with the dedicated power delivery network. Circuit structures and design methodologies of such voltage converters and power management circuits are proposed, and an on-silicon realization is to be implemented in 28nm Fully Depleted Silicon. The results of the research project are expected to achieve more efficient power-conversion as compared to the existing techniques and lower power supply noise as compared to off-chip solutions. The proposed project will advance the state-of-the-art in on-chip voltage regulator and power delivery designs, which will benefit both industry and broader community. The research results will be published in premier conferences and journals for the dissemination of knowledge. A number of students will be trained during the project period, and the nature of the collaboration with industry will poise them in the right position for working in this field in the future. *
Programme
Collaborative Research and Development Grants
Bénéficiaire
Emplacement
Saskatchewan, Canada
Type de bénéficiaire
Academia
Type
Grant
Source
NSERC's Awards Data
Tel que publié
Application id
513704-2017
Name nom
Chen, Li
Department département
Electrical & Computer Engineering
Organization id
16
Institution établissement
University of Saskatchewan
Province en
Saskatchewan
Province fr
Saskatchewan
Country en
CANADA
Country fr
CANADA
Fiscal year exercice financier
2018
Competition year année de concours
2017
Award amount
75453
Program id
CRDPJ
Program name en
Collaborative Research and Development Grants
Program name fr
Subventions de recherche et développement coopérative
Group en
Research partnerships programs
Group fr
Programmes de partenariat
Committee code
96
Committee name en
RPP Internal Decision Cttee
Committee name fr
Cté de décision interne - PPR
Area of application code
514
Area of application group en
Manufacturing processes and products
Area of application group fr
Procédés et produits industriels
Area of application en
Communications equipment
Area of application fr
Matériel de télécommunications
Research subject code
2506
Research subject group en
Electrical and electronic engineering
Research subject group fr
Génie électrique et électronique
Research subject en
Electron devices
Research subject fr
Dispositifs électroniques
Partie
2
Nb partie
2
Application title
On-chip voltage regulation in advanced technologies
Keyword
NSERC
Application summary
The scaling of silicon technologies has enabled multi-billions of transistors in a single chip, which increases the transistor density and operating frequency of the electronics while reducing the cost and energy consumption per transistor. However, this also imposes a significant challenge in power conversion, delivery and management with minimal power loss and noise. For example, only a fraction of the transistors on a large integrated circuit can operate at full voltage/frequency to not exceed the thermal design power, and a large proportion of the circuit blocks is either inactive or in a reduced-power state at any given time to satisfy the power and thermal constraints. This utilization limitation has urged the semiconductor community to develop more efficient power conversion and distribution circuits. The overall objectives of the research project are to optimize voltage regulator-converter circuits and power distribution networks to minimize the power loss during voltage conversion and the noise throughout the power delivery network in power management. The given objectives require power management circuit to be on the same die and optimized together with the dedicated power delivery network. Circuit structures and design methodologies of such voltage converters and power management circuits are proposed, and an on-silicon realization is to be implemented in 28nm Fully Depleted Silicon. The results of the research project are expected to achieve more efficient power-conversion as compared to the existing techniques and lower power supply noise as compared to off-chip solutions. The proposed project will advance the state-of-the-art in on-chip voltage regulator and power delivery designs, which will benefit both industry and broader community. The research results will be published in premier conferences and journals for the dissemination of knowledge. A number of students will be trained during the project period, and the nature of the collaboration with industry will poise them in the right position for working in this field in the future. *