Grant: Collaborative Research and Development Grants

Field-Programmable Gate Arrays (FPGAs) are popular devices which can be programmed to behave like a custom logic chip, but they come with large delay and area (per-chip cost) overheads. In this project, we will investigate electronic design algorithms to reduce congestion and reduce delay found in digital logic circuits that are mapped into FPGAs. In particular, we will examine ways of quickly estimating routing congestion and non-greedy iterative improvement algorithms to reduce peak interconnect demand and circuit delay. The goal is to facilitate production of lower-cost FPGA devices which have lower delay overheads, making them more attractive as a replacement technology to custom chip design.This work will result in lower-cost and faster FPGA devices, to the benefit of all firms designing products that use digital logic, both inside Canada and out.  Designers will also benefit generally from the use of congestion estimation techniques: designs can be mapped into FPGAs more quickly, speeding product development and debugging, resulting in faster time-to-market.  The skills developed by the HQP include advanced algorithm design and heuristic optimization techniques, which are generally useful in many fields in Canada. As well, the FPGA industry (primarily Actel, Altera, and Xilinx) has found a wealth of highly-skilled FPGA talent in Canada, so they have established Canadian R&D centres and hired Canadian graduates to remain in Canada.