Grant: Discovery Grants Program - Individual

Driven by the rapid growth of the Internet, communication technologies, pervasive computing, automobiles, airplanes, wireless and portable consumer electronics, embedded systems have moved from a craft to an emerging and very promising discipline in today's electronic industry. Testing of a fabricated chip is a process that applies a sequence of inputs to the chip and analyzes the chip's output sequence to ascertain whether it functions correctly. As the chip density grows to beyond millions of gates, embedded system testing becomes a formidable task. Vast amounts of time and money have been invested by the semiconductor industry just to ensure the high testability of products. On the other hand, as design complexity drastically increases, current gate-level design and test methodology alone can no longer satisfy stringent time-to-market requirements. The proposed High-Level Test Synthesis (HLTS) system will develop new systematic built-in, self-testable techniques to integrate testability consideration into the synthesis process, and make it possible for an automatic synthesis tool to predict testability of the synthesized circuits accurately in the early stage. It also optimizes the designs in terms of test cost, as well as performance and hardware area cost. Additionally, the proposal targets another problematic consideration affecting the design of systems-on-chip and embedded systems, namely the power consumption. All the existing research, including my previous work on high-level synthesis approaches, has considered low power and testability as two separate optimization objectives. I am planning to extend the above built-in, self-testable synthesis system for low-power dissipation. It is anticipated that a data path allocation and integrated synthesis algorithms (with scheduling and allocation) will be developed to achieve a fully self-testable design and low power dissipation without resulting performance degradation and with minimal area overhead.