Grant: Collaborative Research and Development Grants
Carleton University
$40,000.00
Advanced Frequency Synthesizer Design
EF 2013-14
Résumé
In this research project, advanced frequency synthesis techniques will be explored. Recently, all digital phase-locked loops (ADPLLs) have attracted significant interest due to their small area, better immunity to external noise, simplicity of design, and scalability with process technology. However, the phase noise of the ADPLL typically falls short compared to conventional analog PLLs. Noise performance of the ADPLL is determined by phase granularity and resolution, non-linearity in the loop, and non-idealities of the loop components such as the phase detector and the oscillator. Improvements at the system level must be undertaken while ensuring that requirement of noise, settling time, frequency lock range, phase resolution and power consumption are met. Typically, calibration techniques are required to compensate for process, power-supply voltage, and temperature variations. In addition to noise, unwanted signals (spurs) which are often the result of nonlinearity and mismatch, have to be filtered out to prevent interference with desired signals. At the component level, each block must be designed to reduce non-idealities such noise and nonlinearity. The objective of this project is to explore new design techniques to improve the ADPLL while maintaining its excellent qualities and advantages. The main focus will be on improving the noise performance of the high-speed ADPLLs by employing new techniques both at the system level and at the component level. Working closely with our industrial partner will ensure that our design is practical and will fit in with their larger scale project. Having an improved ADPLL in their portfolio will strengthen their position as the world leader in this field. This is expected to have an impact on their portion of the global market share in this area, and by the successful introduction of related products, will potentially lead to more employment opportunities in Canada. Through publication of the technological advancements in this project, knowledge will be distributed throughout the academic community leading to international recognition for Carleton University and for the researchers involved, advancing the state-of-the-art of the design techniques used in this field.
Programme
Collaborative Research and Development Grants
Bénéficiaire
Emplacement
Ontario, Canada
Type de bénéficiaire
Academia
Type
Grant
Source
NSERC's Awards Data
Tel que publié
Application id
452471-2013
Name nom
Plett, Calvin
Department département
Electronics
Organization id
23
Institution établissement
Carleton University
Province en
Ontario
Province fr
Ontario
Country en
CANADA
Country fr
CANADA
Fiscal year exercice financier
2013
Competition year année de concours
2013
Award amount
40000
Program id
CRDPJ
Program name en
Collaborative Research and Development Grants
Program name fr
Subventions de recherche et développement coopérative
Group en
Research partnerships programs
Group fr
Programmes de partenariat
Committee code
96
Committee name en
RPP Internal Decision Cttee
Committee name fr
Cté de décision interne - PPR
Area of application code
514
Area of application group en
Manufacturing processes and products
Area of application group fr
Procédés et produits industriels
Area of application en
Communications equipment
Area of application fr
Matériel de télécommunications
Research subject code
2519
Research subject group en
Electrical and electronic engineering
Research subject group fr
Génie électrique et électronique
Research subject en
Microelectronics
Research subject fr
Microélectronique
Partie
1
Nb partie
2
Application title
Advanced Frequency Synthesizer Design
Keyword
NSERC
Application summary
In this research project, advanced frequency synthesis techniques will be explored. Recently, all digital phase-locked loops (ADPLLs) have attracted significant interest due to their small area, better immunity to external noise, simplicity of design, and scalability with process technology. However, the phase noise of the ADPLL typically falls short compared to conventional analog PLLs. Noise performance of the ADPLL is determined by phase granularity and resolution, non-linearity in the loop, and non-idealities of the loop components such as the phase detector and the oscillator. Improvements at the system level must be undertaken while ensuring that requirement of noise, settling time, frequency lock range, phase resolution and power consumption are met. Typically, calibration techniques are required to compensate for process, power-supply voltage, and temperature variations. In addition to noise, unwanted signals (spurs) which are often the result of nonlinearity and mismatch, have to be filtered out to prevent interference with desired signals. At the component level, each block must be designed to reduce non-idealities such noise and nonlinearity. The objective of this project is to explore new design techniques to improve the ADPLL while maintaining its excellent qualities and advantages. The main focus will be on improving the noise performance of the high-speed ADPLLs by employing new techniques both at the system level and at the component level. Working closely with our industrial partner will ensure that our design is practical and will fit in with their larger scale project. Having an improved ADPLL in their portfolio will strengthen their position as the world leader in this field. This is expected to have an impact on their portion of the global market share in this area, and by the successful introduction of related products, will potentially lead to more employment opportunities in Canada. Through publication of the technological advancements in this project, knowledge will be distributed throughout the academic community leading to international recognition for Carleton University and for the researchers involved, advancing the state-of-the-art of the design techniques used in this field.