Grant: Discovery Grants Program - Individual

Low power consumption is one of the most important design factors for embedded systems, especially in this global warming era. Besides the computing elements, the memory access, communication over system bus or network links and device access all consume energy which cannot be neglected. Therefore, low-power design should consider the system-level energy consumption. Most system-level energy scheduling algorithms focus on systems with single CPU or homogeneous systems. Advanced embedded systems are becoming more and more complex. They are networked and may be composed of subsystems with various processors like single-core processors, multi-core processors, GPU, E-Textiles, etc. The networked and heterogeneous nature of such systems poses a great challenge on system-level low-power design. In this project, we will investigate new techniques to design system-level, low-power scheduling algorithms for networked heterogeneous embedded systems. The effect of various high-level architecture features, system connections, as well as scheduling policies for system-level energy, will be studied. A framework will be proposed to specify system models and constraints and to design system-level, low-power scheduling algorithms. The specifications of the system model include the task model, the energy model, the resource model, the energy model of the devices and batteries, reliability and security constraints, etc. Existing DVS scheduling and low-power management algorithms will be studied and adapted, and new system-level energy minimization algorithms will be developed for various configurations of the system. The proposed techniques and framework will be tested and evaluated, based on simulation environments. The results of this project will make contributions for low-power embedded system designs and can be applied to the information technology industry, such as health monitoring systems and smart security devices.